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8 Mbit LPC Flash
A Microchip Technology Company
SST49LF080A
Data Sheet
Toggle Bit (DQ 6 )
During the internal Program or Erase operation, any consecutive attempts to read DQ 6 will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is
valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block-, or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 21 for Toggle Bit tim-
ing diagram and Figure 35 for a flowchart.
Table 10: Operation Modes Selection (PP Mode)
Mode
Read
Program
Erase
RST#
V IH
V IH
V IH
OE#
V IL
V IH
V IH
WE#
V IH
V IL
V IL
DQ
D OUT
D IN
X 1
Address
A IN
A IN
Sector or Block address,
XXH for Chip-Erase
Reset
Write Inhibit
Product Identification
V IL
V IH
X
V IH
X
V IL
X
V IL
X
X
V IH
V IH
High Z
High Z/D OUT
High Z/D OUT
Manufacturer’s ID
(BFH) Device ID 2
X
X
X
See Table 11
T10.0 25026
1. X can be V IL or V IH , but no other value.
2. Device ID = 5BH for SST49LF080A
Data Protection (PP Mode)
The SST49LF080A devices provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle.
V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadver-
tent writes during power-up or power-down.
Software Data Protection (SDP)
The SST49LF080A provides the JEDEC approved Software Data Protection scheme for all data alter-
ation operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of a six-byte load sequence.
?2011 Silicon Storage Technology, Inc.
19
DS25086A
11/11
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